Reliability and Qualification

Memberships and Certifications

Cirrus Logic is a member of industry standard and quality professional organizations. We actively participate in industry standard development as part of AEC and JEDEC.

Reliability and Qualification Test Description

1. What is Reliability?

Reliability is the probability that an item will perform the required function under stated conditions for a designated period of time. Reliability in semiconductor devices is, in two words, the Survival Rate. It is the proportion of devices used from time zero that will not have failed by a given time ‘t’.

2. Cirrus Logic Quality and Reliability

Cirrus Logic strives to achieve the highest quality and reliability performance on all our products through a systematic approach. We emphasize quality and reliability at every phase of the product: from product design/development, fabrication, assembly, testing and out-going quality control. Our qualification/reliability testing is used to ensure all the products are below targets set for Early Failure Rates in PPM and Wear-Out Failures in FITs.

3. Reliability Failures

The bathtub curve is a standard way to picture the types of failures during a device’s life time. There are two basic types of failures, Early Failures and Wear-Out Failures. During the normal operation of the device operation, that is the section between early failures and wear out, the failure rate is normally constant and at an extremely low rate.

4. Cirrus Logic Reliability Categories

Cirrus Logic reliability tests can be divided into two categories: qualification and monitoring.

    a. Qualification:

       1. Purpose: New products are tested for manufacturability.
       2. Performed for fab, technology, packages, and assemblies.

    b. Monitoring:

       1. Purpose: Existing devices are periodically tested to ensure that manufacturability remains at a high standard of Reliability and Quality.
       2. Performed for fab, technology, packages, and assemblies.

5. What is a Failure Rate?

Failure rate is a typical measure of reliability. It expresses the probability that a device which was “good” until a given time and will fail in the next instant. The measures used at Cirrus Logic to describe a device’s reliability;

• Percentage: number of device failed divided by the total number of samples in consideration expressed in percentage.

• FITS (Failure in time per billion device hours): the number of defects per 109 samples.

• DPM (DPPM): the number of defects (defect parts) per million devices.

• Confidence interval: χ 2 with a chosen confidence level (normally, 60%) is used as a weight in calculating failure rates. It is especially useful when zero failures are observed in the limited sample sizes.

Reliability Stress Test Description

The following is a list of the typical stress tests performed by Cirrus Logic.

Test conditions follow Cirrus Logic Integrated Circuit Qualification Specifications, applicable JEDEC standards, or AEC Q100. Wherever conflicts arise, JEDEC is followed for commercial product and AEC is followed for automotive products. For Board Level Reliability, IPC-9701 is used as a reference standard.

Devices which undergo the following stress tests are required to pass the same electrical and functional test throughout. Failure analysis is required and root of causes should be identified and corrective actions followed as necessary.

1. Operating Life (JEDEC JESD22-A108)

Operating life is an intense stress test performed to accelerate thermally activated failure mechanisms through the application of extreme temperature and dynamic voltage biasing conditions. Typically it is performed at 125°C with a bias level at the maximum data sheet specifications.

a. Infant Life

Failure rate is higher during the initial use due to random defects, the variation of the production process, etc. Infant/Early life test is performed to estimate the failure rate, usually measured by DPM, during that period of time (three month to six months). Infant life test is normally a reliability measure to the fab process used for the device. Early failure rate (EFR) is controlled by production burn-in or elevated voltage stress until the design and/or fab process is made more robust.

Purpose: a continuous voltage (device specific) is applied to the device at 125°C for various lengths of time. Infant mortality rates or early failure rates are calculated and the length of production burn-in is determined from the results of the test.

Description: conditions of maximum VSSs, I/O loading, clock rate vectors applied to exercises the maximum amount of digital circuitry, and appropriate stimulus to exercises analog full scale ranges applied to the device at 125°C for various lengths of time.

Elevated voltage testing is a method to screen out weak parts by providing a higher than normal supply voltage for a short period of time.

b. High Temperature Operating Life (HTOL)

The operating life failure rate period generally continues for a considerably longer time. HTOL is used to determine device resistance to prolonged operating stress, including both electrical and thermal mechanism. HTOL is normally a reliability measure for the design/layout of the device in a given fab process.

Purpose: to simulate the operating lifetime under a specified set of conditions.

Description: same as Infant life.

2. Preconditioning (Precon) (JESD22-A113 / IPC/JEDEC J-STD-020)

Purpose: to simulate “real life” PC board assembly process

Description: Packaged components are subjected to dry bake, moisture soaking, solder reflow simulation and electrically testing using Automated Test Equipment (ATE) before reliability testing. This stress is performed prior to package reliability qualification tests (HAST / THB, TC, UHAST).

Variables: Bake = 125°C / Moisture Soak = 30°C / 60%RH / Reflow Temperature = 260°C. Other conditions may be used.

3. Biased Highly Accelerated Stress Test (HAST) (JESD22-A110)

Purpose: to simulate extreme operating conditions (Very similar to THB).
Description: Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are subjected to bias while the devices are in the chamber. The devices are then electrically tested using ATE for electrical failures. Variables: Temp = 130°C or 110°C / Humidity = 85% RH/ Time = 96 or 264 hours, voltage bias levels.

4. Temperature Humidity Bias (THB) (JESD22-A101)

Purpose: to determine device/package resistance to prolonged temperature, humidity, and electrical stress.

Description: Devices are baked in an oven at an extreme temperature and humidity conditions for various lengths of time. The devices are subjected to maximum differential bias on alternating pins while the devices are in the oven. The devices are then ATE tested for electrical failures.

Variables: Temp = 85°C / Humidity = 85% RH / Time = 1000 hours (interim read points are 100 and 500 hours), voltage bias levels.

5. Temperature Cycle (TC) (JESD22-A104)

Purpose: typically accelerates the effects of thermal expansion mismatch among different material of the package and circuit. It is used to determine package resistance to high and low temperature and to temperature changes during transportation and use.

Description: Devices are placed in a thermal chamber. A temperature cycle is defined by the temperature extremes, dwell/soak time at the extremes and the temperature ramp rate. The devices are electrically tested afterwards. Failed devices are checked for stress cracks on injection molding or epoxy used for die mounting, delamination, etc.

Variables: Temp = 150°C (top) and -65° C (bottom) / Time = 10 minutes per chamber, number of cycles = 500. Other equivalent conditions may be used.

6. Unbiased Highly Accelerated Stress Test (UHAST) (JESD22-A118)

Purpose: to simulate extreme operating conditions. (Similar to Autoclave).

Description: Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are then ATE tested for electrical failures.

Variables: Temp = 130°C or 110°C / Humidity = 85% RH/ Time = 96 or 264 hours

7. HTSL (JESD22-A103)

Purpose: Used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices.

Description: Devices are baked in a chamber at an extreme temperature and humidity for various lengths of time. The devices are then ATE tested for electrical failures.

Variables: Temp = 150°C / Time = 1000 hours. Other equivalent conditions may be used.

8. ESD

This stress is used to determine the Electrical Static Discharge (ESD) sensitivity for a semiconductor device. The following are three commonly used models of tests. ESD test types:

a. Human body model (HBM) (JS-001)

Models the discharge of electricity into a pin on a device through contact with a human body that has been charged with static electricity. Equivalent capacitance of the discharge circuit C=100pF and resistance R=1.5 km.

b. Charged device model (CDM) (JESD22-C101)

Models the discharge of electricity which occurs after an area such as the device package or lead frame becomes charged due to handling, and a pin on the device then contacts a metal apparatus or fixture. It has been found that this model shows good correlation with the breakdown mode on automatic assembly lines.

9. Latch-UP (JEDEC 78)

Latch-Up testing performed to ascertain whether a device can sustain SCR latch-up due to DC current injected into the input and I/O pins. Current injections as well as power supply over voltage are tested at Cirrus Logic. Products subjected to Latch-UP must pass ATE electrical testing following stress.

a. Latch-UP I/O:

Variables: Injection current +-(0 to 100) mA, temperature, 25°C or high max of the specified temperature on data sheet.

b. Latch-UP Vdd

Variables: Power supply tested at 1.5*Vddmax, temperature, 25°C or high max of the specified temperature on data sheet.

Board Level Reliability

For advanced / emerging package technologies, board level reliability (BLR) testing may be conducted to determine the solder joint interconnect reliability using daisy-chained test vehicles. Failure analysis is conducted on failed samples to determine the cause.

1. Thermal Cycle (BLR TC) (JESD22-A104 / IPC-9701)

Purpose: accelerates the effects of thermal expansion mismatch between the component solder joint and the system board.

Description: Daisy-chained test devices are soldered to daisy-chain printed circuit boards. These boards are then placed in a thermal chamber. A thermal cycle is defined by the temperature extremes, dwell/soak time at the extremes and the temperature ramp rate. The resistance of all daisy chain nets are measured either in-situ or following pre-defined read points and compared to the initial resistance.

Variables: Temp = 85°C (top) and -40° C (bottom) / Time ~ 60 minutes per cycle, number of cycles = 1000. Other equivalent conditions may be used.

2. Mechanical Shock (BLR MS) (JESD22-B110 / JESD22-B111)

Purpose: to simulate failure modes observed during product/system level test and handling, transportation or field operation by evaluating the shock performance of the component mounted to the system board.

Description: Daisy-chained test devices are soldered to daisy-chain printed circuit boards. These boards are then placed on a shock testing tool that is capable of providing shock pulses with required peak acceleration and pulse durations. The resistance of all daisy chain nets are measured following pre-defined read points and compared to the initial resistance.

Variables: Acceleration pulse = half-sine waveform / Peak Acceleration = 1500G or 2900G impacts with PCB bending / number of shocks = 30. Other conditions may be used.