Fractional-N Clock Multiplier

The CS2501 is a system-clocking device incorporating a programmable phase-locked loop (PLL). The hybrid analog/ digital PLL architecture comprises a delta-sigma fractional-N analog PLL and a digital frequency-locked loop (FLL). The CS2501 enables clock generation from a stable timing reference clock. The device can generate low-jitter clocks from a noisy clock reference at frequencies as low as 50 Hz. An internal oscillator can provide the timing reference clock, enabling a reduction in external component requirements.

The CS2501 can be configured using a control interface supporting I²C and SPI modes of operation. The CS2501 can be powered from a single 1.8 V or 3.3 V supply. The device combines high performance with low power consumption.

The CS2501 is available in commercial-grade 10-pin TSSOP package for operation from –40°C to +85°C. The device is also available in the AEC-Q100-qualified grade-2 package for operation from –40°C to +105°C.

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Technology

Audio Clock Generation and Jitter Reduction

Features

• High-performance analog/digital phase locked loop
• Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL
  • Generates low-jitter 6–75 MHz clock (CLK_OUT), synchronized to a 50 Hz–30 MHz low-quality or intermittent frequency reference (CLK_IN)
• Flexible timing reference source
  • External clock, external crystal or built-in oscillator
• Great performance
  • High resolution PLL ratio (1 PPM)
  • 40 psRMS period jitter
  • 35 psRMS period jitter with internal reference
• Glitchless clock output generated from intermittent input
• I²C/SPI control port
• Configurable auxiliary clock/status output
• Minimal board space required
  • No external analog loop-filter components
• Pin-to-pin, register map, and control compatible with CS2100 and CS2300
• Single-supply operation at 1.8 V or 3.3 V

Parametric Specifications

Host Interface	true
One-Time-Programmable	false
Frequency Synth / Clock Generator	false
Clock Multiplier / Jitter Removal	true
Power Supply (V)	1.8; 3.3
Input Frequency Range	50 Hz to 30 MHz
Reference Frequency Range (MHz)	8-75
Output Frequency Range (MHz)	6-75
Package	10L-TSSOP

Technical Documents

CDB-CLOCKING User Guide

Jun 1, 2024, DS1386DB1 : 2.7 MB

CDB-CLOCKING-MB Schematic and Block Diagram

Jun 1, 2024, CDB-CLOCKING-MB-REV-B : 715KB

CDB2501-DC-SD Schematic Layout

770 KB

CS2501 Product Data Sheet

Nov 1, 2024, DS1345A4 : 2.1 MB

CS2501 Migration Document

May 1, 2024, AN0631R1 : 144 KB

CS2500, CS2501, and CS2600 for Automotive Audio Networks

Mar 1, 2024, AN0622R1 : 141.9 KB

CS2XXX Device ID Compatibility

Mar 1, 2024, AN0626R1 : 90 KB

Software and Tools

Press Releases

2024

Dec 05

Cirrus Logic Redefines Timing for Automotive Audio and Pro Audio Systems

Next-Generation Timing Devices Deliver Elevated Performance, with Seamless Upgrade for all Existing Cirrus Timing Devices

Block Diagram

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