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The CS5101A and CS5102A are 16-bit, monolithic CMOS analog-to-digital (A/D) converters capable of 100 kHz (CS5101A) and 20 kHz (CS5102A) throughput. The low power consumption of 44 mW, coupled with a power-down mode, makes the CS5102A particularly suitable for battery-powered operation. On-chip, self-calibration circuitry achieves nonlinearity of ±0.001% of FS and guarantees 16-bit no missing codes over the entire specified temperature range. Superior linearity also leads to 92 dB S/(N+D) with harmonics below -100 dB. Offset and full-scale errors are minimized during the calibration cycle, eliminating the need for external trimming. The CS5101A and CS5102A each consist of a 2-channel input multiplexer, digital-to-analog converter, conversion and calibration microcontroller, clock generator, comparator and serial communications port. The inherent sampling architecture of the device eliminates the need for an external track-and-hold amplifier. Each converter's 16-bit data is output in serial form with either binary or 2's complement coding. Three output timing modes are available for easy interfacing to microcontrollers and shift registers. Unipolar and bipolar input ranges are digitally selectable. |
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| Resolution (bits) | Throughput (Sps) | Integral Linearity (%FS) | Differential Linearity (±LSB) | Dynamic Range (dB) | Power Consumption (mW) | Package |
|---|---|---|---|---|---|---|
| CS5101A | ||||||
| 16 | 100 | 0.0015 % | NMC | 92 | 320 | 28 PLCC |
| CS5102A | ||||||
| 16 | 20 | 0.0015 % | NMC | 92 | 44 | 28 PLCC |
The CS5101A and CS5102A are 16-bit, monolithic CMOS analog-to-digital (A/D) converters capable of 100 kHz (CS5101A) and 20 kHz (CS5102A) throughput. The low power consumption of 44 mW, coupled with a power-down mode, makes the CS5102A particularly suitable for battery-powered operation.
On-chip, self-calibration circuitry achieves nonlinearity of ±0.001% of FS and guarantees 16-bit no missing codes over the entire specified temperature range. Superior linearity also leads to 92 dB S/(N+D) with harmonics below -100 dB. Offset and full-scale errors are minimized during the calibration cycle, eliminating the need for external trimming.
The CS5101A and CS5102A each consist of a 2-channel input multiplexer, digital-to-analog converter, conversion and calibration microcontroller, clock generator, comparator and serial communications port. The inherent sampling architecture of the device eliminates the need for an external track-and-hold amplifier.
Each converter's 16-bit data is output in serial form with either binary or 2's complement coding. Three output timing modes are available for easy interfacing to microcontrollers and shift registers. Unipolar and bipolar input ranges are digitally selectable.
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